To implement a set of desirable logic functions, an integrated circuit (“IC”) designer typically uses variety of options or approaches to achieve such functions using, for instance, conventional semiconductor ICs. Conventional semiconductor IC, for example, includes application-specific ICs (“ASICs”) and/or programmable logic devices (“PLDs”) or field programmable gate arrays (“FPGAs”). ASIC is a semiconductor fabricated chip typically containing various circuits specifically customized or configured to perform a designated set of function(s) and/or purpose(s). ASIC chips generally provide efficient performance with fast clock cycles. Since ASIC is customized for a particular functionality, a drawback associated with the ASIC chip is unalterable after the chip is fabricated.
PLDs or FPGA, on the other hand, is alterable after the chip is fabricated because an FPGA can be programmed to perform a user designated specific function. A typical PLD or FPGA includes multiple programmable logic blocks, routing resources, and input/output (“I/O”) pins. An IC designer is able to select a desirable logical function(s) for the FPGA to perform. Although a PLD or FPGA is more versatile or flexible, it is typically high cost (large die size), high power consumption, and relatively low performance partially because it operates relatively low clock cycles or speed. A drawback associated with a typical PLD or FPGA is relatively low speed as well as excessive power consumption.
With increasing demand in high performance, power conservation, as well as some degree of functional flexibility, an IC combining ASIC and FPGA is proposed to leverage unique features of both ASIC and FPGA for optimizing IC performance. A problem, however, associated with such combination of ASIC and FPGA is communication between ASIC and FPGA since ASIC and PLD typically operate in different clock domains. For example, ASIC typically operates clock cycles faster than clock cycles used by FPGA.
A conventional approach to mitigate clock differences is to provide an asynchronous first-in first-out (“FIFO”) buffer between FPGA and ASIC for decoupling FPGA clock domain from ASIC clock domain. A problem associated with this approach is added latency for data flows between FPGA and ASIC. For certain applications, such added latency is not acceptable.